1. Field of the Invention
The invention relates to a method for fabrication metal-oxide semiconductor transistors.
2. Description of the Prior Art
With progress in the semiconductor industry, performance and economic factors of integrated circuit design and manufacture have caused a scale of devices in integrated circuits to be drastically reduced to miniaturized sizes, increasing density on a chip. However, a short channel effect, which results in a poor threshold voltage roll-off characteristic, always accompanies miniaturization. To avoid this problem, industries have provided a method for forming lightly doped drains (LDDs) having an ultra shallow junction as a solution.
In a conventional ultra shallow junction formation, a low energy ion implantation process is performed in a shallow surface of a substrate adjacent to two sides of a gate structure, a rapid thermal annealing (RTA) process is then performed to form a junction profile. However, as device scale is reduced to 90-nm and smaller, the conventional ultra shallow junction formation hits a limitation in depth control, and co-implantation performed in cooperation with pre-amorphorization (PAI) and laser annealing seems to be able to satisfy demands down to 65-nm and even 45-nm processes.
Please refer to FIGS. 1-3. FIGS. 1-3 illustrate a method of utilizing pre-amorphorized implantation process for fabricating a p-type metal-oxide semiconductor (PMOS) transistor having ultra-shallow junction according to the prior art. As shown in FIG. 1, a semiconductor substrate 100 having a gate structure 102 thereon is provided, in which the semiconductor substrate 100 can be a semiconductor wafer or a silicon on insulator substrate. The gate structure 102 includes a gate dielectric 104 and a gate 106 disposed on the gate dielectric 104. Next, a pre-amorphorized implantation process is conducted by injecting atoms such as antimony (Sb) or germanium (Ge) into the semiconductor substrate 100. The pre-amorphorized implantation specifically disrupts the lattice structure of the semiconductor substrate 100 and forms an amorphorized region 108 in the semiconductor substrate 100.
Next, as shown in FIG. 2, an ion implantation process is performed by implanting a p-type dopant such as boron (B) or boron fluoride (BF2) into the semiconductor substrate 100 surrounding the gate structure 102. A rapid thermal annealing process is conducted thereafter to form a lightly doped drain 110 having ultra-shallow junction of a PMOS transistor.
As shown in FIG. 3, a spacer 112 is formed on the sidewall of the gate structure 102. Next, another ion implantation process is performed to inject a p-type dopant with higher concentration into the semiconductor substrate 100 surrounding the spacer 112. The p-type dopant can be the aforementioned boron or boron fluoride. Another rapid thermal annealing process is performed thereafter by using a temperature between 950 degrees to 1000 degrees to activate the dopants and form a source/drain region 114 in the semiconductor substrate 114.
It should be noted that despite the fact that the conventional pre-amorphorized implantation process can be conducted to achieve ultra-shallow junctions by injecting non-doping ions for inhibiting the diffusion of dopants implanted thereafter, the implantation process also creates significant interstitial defects while using the implanted ions to damage the lattice structure of the silicon substrate. Specifically, the interstitial defects become diffusion paths for dopants such as boron and ultimately causes a transient enhanced diffusion effect. This transient enhanced diffusion effect not only deepens the junction profile but also makes the distribution of the dopant not sheer in the lateral direction, resulting in an end of range dislocation phenomenon and a severe short channel effect.